Is there a specific way to stop the test/simulation in case condition failure?

I want the test to stop in the case of a failure condition. I used UVM_ERROR, but this only produces a text message. Is there a specific way to stop the test/simulation in case condition failure in addition to the text message (something like assert in systemVerilog)?

I want the test to stop in the case of a failure condition. I used UVM_ERROR, but this only produces a text message. Is there a specific way to stop the test/simulation in case condition failure in addition to the text message (something like assert in systemVerilog)?

0

1 Answer

Add the +UVM_MAX_QUIT_COUNT=1 runtime option on your simulator command line. This will end the simulation after the 1st UVM_ERROR.

0

ncG1vNJzZmirpJawrLvVnqmfpJ%2Bse6S7zGiorp2jqbawutJoa2lpY2WEcYKOoqpmrJiav6Z5wGaqqZ2TnrOqr4ywmLJlpKR6tMDOqWStoJViwaa%2F02aqoqWloa61tc6nZKKmXZiutLGMnKannJmptrC6jJ%2BYoqSlp7I%3D

 Share!